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Projects Executed

Verification Consulting Services :

Project 1

USB3.0 Hub SoC verification using UVM

  • Methodology consultancy.
  • Implemented VIPs for GPIO, JTAG and Scoreboards.

Project 2

Wireless 802.11ac MAC IP Verification using UVM

  • Turn Key project.
  • Building complete verification environment and functional models of STAs.
  • Verification Planning and Simulation management.

Project 3

Verification of 802.11ac WiFi SoC

  • 802.11ac compliant MAC IP level verification.
  • Used AXI master and slave to interface MAC input.
  • Used in house MAC UVM VIP for simulation of multiple stations.
  • Verified dual core MAC where 2.4 GHz and 5 GHz bands are simultaneous SoC Level Verification.
  • Reused 90% of core level components and tests.
  • Verified MAC, PHY & RADIO with PCIe end point as host interface.
  • Chip contained latest AXI-4 NIC.
  • Integrated PCIe UVM VIP.

Project 4

Verification of ARM based Dual Core SoC using UVM

  • ARM Cortex-M4 and Cortex-M0 based ASIC with custom blocks for hardware accelerated FFT and other Math functions.
  • Highly stringent verification plan for block level and chip level.
  • UVM based constrained-random, easily configurable, reusable block-level Testbenches development for new blocks. Used Cadence AMBA VIPs for the same.
  • Testbenches designed to be easily configurable and reusable at different levels of hierarchy. Complexity was absorbed by testbench to provide ease of writing testcases with minimal code.
  • Integration of block-level environments into legacy chip-level environment with custom wrappers for legacy non-UVM block-level environments.

Project 5

Verification of ARM Cortex M4 based DSP Processor

  • Worked on the peripherals of DSP Processor like UART, CRC, SMC, TIMER, ROTARY, EMAC and MDMA etc.
  • Ported the Legacy tests of Peripherals to C for ARM core and debugged the failures.
  • Worked on writing tests for corner cases of Peripherals.
  • Worked with assertions for Peripherals and Memories.
  • Debugging of testcases and Legacy tests.

Project 6

Verifications of Digital core of a MEMS ASIC using VMM and VCS

  • Porting the legacy VMM testbench to the new design requirements.
  • RAL maintenance.
  • Creation of new components in environment for higher efficiency and better self-test capability.
  • Creation of Test plan and Testcases with respect to coverage.
  • Regressions running for RTL and gate level simulations, Report generation for the same.

Project 7

Verification of RoC (Raid on Chip)

  • Verified 3 versions of SoC with blocks like CCR, SAS, MSS, PBAM, IOP, PCI, OCM, etc.
  • UVM Methodology.
  • Challenging Chip level Verification including the whole SoC, buses and the interconnect.

Project 8

SoC Verification (3 cores)

  • SoC had 3 cores (2 internal and 1 ARM) and 60 peripherals.
  • Verified the blocks using VMM Random test generation and directed DV.
  • Fault analysis and coverage along with negative tests.
  • Gate level setup and simulations.
  • PTE simulation support.

Project 9

Building verification environment using UVM for QoS engines used in 4G Networks.

Project 10

Verification of Flash and Cache controller blocks for ARM based processor using Systemverilog.

  • Porting the legacy testbench for the new design requirements.
  • Cache and Flash memory functional modeling using SV.
  • Creating Testplan and testcases with respect to coverage.
  • Developing Regression scripts and report generating scripts.

Project 11

Verification of Serdes PMD and Repeater Cores

  • Verification of 28 and 16nm cores supporting multiple data rates up to 28.125 Gbps.
  • IEEE PCS or other coding layer compliant IP level verification.
  • Verification environment custom built to support different lane speeds, over sampling rates, tuning of multiple PLLs, mapping of logical and physical lanes.
  • Verification of arbitrary lane addressing based on different clock domains.
  • Verification of MDIO block. MDIO Management interface supports IEEE clause 22/45 with maximum speed of 25 MHz.
  • Verification of ARM M0 which has integrated program RAM, interfaced to core using parallel management interface.