Aceic Design Technologies is a technology focused company and we offer superior ASIC verification services, especially for creating class based verification environments using SystemVerilog, UVM, OVM and VMM.
Our engineers are exposed to the best of design technologies, verification methodologies and EDA tools.
They are groomed to be specialists in key methodologies of verification like UVM, OVM, Assertions etc.
With todays growing Design / Verification challenges & complexities , this USP will help our customers to meet the TTM and ROI goals.
Highly experienced consultants with 20+ years of experience in Semiconductor domain and ASIC verification will accept the complete ownership for verifying your chips and deliver on the engagement successful. Our technical models and technologists, allowing you, 'the customer' to focus on critical aspects of the product and business.
We offer various business models based on your requirements.
Our experience with ACEIC Design Technologies has been nothing but pleasure. Starting from the top, Siva and his team, were very good to work with, accommodating all our requests. They let us interview and chose candidates from their pool, a kind of rarity in the intense competition and a surge in demand that service organizations are experiencing these days. Siva, CEO himself was very informed and knew exactly where the organization is headed. Although a new player in town, talking to them gave me confidence to give them an opportunity. Together we came up with a business model that was a win-win situation for us and it all took off from there.
The engineer from ACEIC is one of the best engineers on the project that we recently executed. Coming on board with virtually no industry experience, he ended up contributing significantly to the project. And in my opinion, the attitude that helped me get there was his ability to focus and dedication. I would see him work for hours, when other engineers were taking breaks. He also was very forthright in asking for help whenever required, so that he keeps his momentum. But at the same time had the prudence to struggle and learn by himself, to make sure that his understanding are cemented. He was also very particular about the schedule and conveying any issues regarding a project in the weekly meeting. Hence he had communication skills. After the project was over, I recommended him to another group and I believe he is still doing wonderfully well. I would like to have him on board again anytime.
The engineer from ACEIC was assigned the Digital Verification of two critical blocks of an SoC. The blocklevel testbench was in VHDL and integrating into chip level SV based environment was a challenge. The engineer successfully integrated the testbench. She also developed a methodology to precompile VHDL design blocks and this was a time saver during compile. It also isolated other engineers from the VHDL aspect of the design and TB. She caught multiple bugs in the integration and raised several questions to the IP vendor that resulted in a better understanding of the design. On the other block, she ramped up quickly on the architecture and handled the trace aspect of it. She came up with a checker to verify trace integrity. She has caught multiple blocks and also raised questions that resulted in better specification.
We also had another engineer working on SoC Digital Verification. He was one of our early adopters of VMM technology. He ramped up quickly and was eventually given the Digital Verification of 5 modules. He always had a complete understanding of the functionality of the module and he was the go-to person for all of these modules. When it was decided to take on a new block of the next version of the same source in the design cycle, he was assigned this DV and he was given a very short timeline. He successfully met the goals set for him in the schedule He caught multiple bugs in the chip and has been involved in the development of DV methodology. His attitude was positive and he was always enthusiastic to take on any activity. He has made a significant contribution to this SoC verification.
The engineers from ACEIC are sharp and intelligent. They are able to grasp requirements quickly. By the kind of queries I get from them, it is evident that they do their homework. They all display good teamwork and leadership qualities. Also, they are very sincere and hardworking. They stretch themselves many a times, helping us meet strict deadlines.
As a Junior engineer, Ram ramped up very quickly in the simulation environment, tools, test setup, etc. His main work was on debugging directed tests and writing assertions. In the space of 6 months that he worked with us, he supported the effort to port assembly language tests to ‘C’ on 4 specific peripherals : UART, SMC, MDMA, CRC. He supported debug of tests of these blocks across RTL simulations, gate level runs and ATE runs (for delivery to tester). Further, he ported system level tests for verifying reserved memory spaces and MDMA transfers to peripheral register areas. He added hand-written tests to the regression suite, of which, I’d like to particularly mention the effort for the tests handling imprecise arm faults. It took interwoven assembly-C and a good understanding of the way the compiler handles the stack to achieve this. The test was used as a template by others
Once he ramped up on the understanding of the tool/environment, I was very impressed by the speed with which he completed tasks, which is evident from the number of jobs he completed. I also appreciate his systematic approach to some tasks like documentation of issues during the porting of tests. Overall, engineer from Aceic has made significant contributions to our project. He has been a dedicated and focused engineer throughout our engagement.